What is the relationship between data converter jitter, phase noise and signal-to-noise ratio (SNR)?

Clock jitter is a problem because it causes uncertainty (noise) in data conversion processing. Time domain jitter is equivalent to phase noise in the frequency domain. Phase noise spreads the power of a part of the clock signal from the fundamental frequency to other frequencies. Since sampling can be equivalent to addition or multiplication in the time domain, that is equivalent to convolution in the frequency domain, this is important. Thus, the spectrum of the sampling clock is convoluted with the spectrum of the input signal. Moreover, since jitter is a wideband noise of the clock signal, it also appears as broadband noise in the sampling spectrum. The sampling spectrum is periodically repeated at the sampling rate, and the broadband noise deteriorates the noise floor characteristics of the analog-to-digital converter (ADC).

1. The encoded signal is convolved with the analog input so that the clock spectrum (left) is represented on the
2. analog signal. Since the ADC is a sampling system, the wideband noise of the sampling clock is also confusing
3. in the additional band (on the right), which causes all broadband noise to enter the coded portion and mix
4. into the Nyquist band.

What equation can be used to analyze the effects of jitter and phase noise on the converter?

To calculate the effect of phase noise on SNR, consider the clock delay equivalent to the phase delay at a given frequency. From the perspective of noise power, this means that the phase noise σ2θ expressed in rms radians is equal to ω2clk time σ2τ, where στ is the phase jitter expressed in rms seconds, and ωclk is the clock frequency in radians/second, so for any Jitter error, the higher the signal frequency, the greater the phase error. The relationship between phase noise and SNR can be defined by the following equation:

\(SHRCLK(dB)=-10logσ2θ\)

1. The plot plots the theoretical SNR over multiple jitter characteristics and the number of significant bits in the
2. case where jitter affects the input frequency. Suppose a simple case where the bandwidth of the clock jitter falls into a single Nyquist zone and excludes quantization noise and thermal noise. In a single-wave system, the SNR of a signal when it is acquired with a jittered clock signal can be expressed as:

\(SHRsig(dB)=1/(4π2σ2τf0)\)

In a multi-carrier narrowband system, the SNR expressed in decibels with reference to one of the carriers (dBc) has the same form, but the sum of all frequency terms is substituted for the f0 term in the denominator. This is important because it increases the level of quantization noise and thermal noise. In these applications, jitter may not contribute much to the overall SNR, and quantization noise and thermal noise dominate. However, in a wideband system, assuming that the data average is zero, there is a flat evenly distributed spectrum between the two frequencies fL and fH, and the SHR can be expressed as:

\(SHRsig=(1/σ2τ)×3/(f2H+fHfL+f2L)\)

What happens when the converter works above the baseband?

In sampling systems where the signal frequency occupies a higher frequency Nyquist zone, the clock signal is required to have better jitter characteristics than the baseband system because if the jitter is large enough, the noise caused by the jitter may be mixed. In-band, in such an application, the upper limit of the SNR caused by jitter can be determined by the following equation:

\(SNR(dB)=-20log(2πfanalogtrmsjitter)\)

Here fanalog is the input frequency and t is the jitter. Given the operating frequency and the required SNR, the following equation can be used to determine the requirements for clock jitter:

\(Tjitter=(10(-snr/20))/2πfanalog\)

Therefore, if jitter is the only limiting factor in converter performance, sampling a 70MHz IF signal with an SNR of 75-dB requires limiting the maximum clock jitter to a level of 400 fs.

What is the difference between synchronous data converters and other digital applications?

In fact, high-speed data converters can tolerate lower jitter or phase noise levels than ultra-high-speed communication systems. For example, the Sonet/SDH specification allows clock jitter on the order of a few picoseconds. However, for a data converter operating at a sampling rate of 100M points per second with an input analog signal frequency between 70 and 200 MHz, the jitter must be less than 1 ps.

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